3.1. Bitwise Logic 1

The instructions AND, ORR, EOR, and MVN function as the bitwise logical operations and, or, exclusive or, and not. These bitwise operations combine either two registers or a register and an immediate by comparing bit 0 of the first to bit 0 of the second, bit 1 of the first to bit 1 of the second, etc…

3.1.1. AND

The AND instruction compares the individual bits of two patterns using logical AND: produce a 1 if both inputs are 1, 0 otherwise. In these two patterns:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	0	0
0				0				0				0				0				0				3				C

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	1	1	0	1
0				0				0				0				0				0				6				D

Bits 2, 3, and 5 are the only ones that are 1 in both - thus this output is produced:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	1	0	0
0				0				0				0				0				0				2				C

ANDrd, rn, rm / #

Combine the bits of rn and the bits of rm or # with AND. Result in rd.

3.1.2. ORR

ORR compares the individual bits of two patterns using logical OR: produce a 1 if either or both inputs are 1, 0 otherwise. In these two patterns:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	0	1	1	0	0
0				0				0				0				0				0				A				C

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	0	0	0	1
0				0				0				0				0				0				F				1

Bits 0, 2, 3, and 4-7 are 1 in at least one of of the two inputs - thus this output is produced:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	0	1
0				0				0				0				0				0				F				D

ORRrd, rn, rm / #

Combine the bits of rn and the bits of rm or # with OR. Result in rd.

---

@AND keeps 1 if both inputs are 1
MOV   r1,      #0x3C             @ r1 = 0000 ... 0011 1100
@              #0x6D                    0000 ... 0110 1101
AND   r2, r1,  #0x6D             @ r2 = 0000 ... 0010 1100 or 0x2C

@ORR keeps 1 from either pattern
MOV   r4,      #0xAC             @ r4 = 0000 ... 1010 1100
MOV   r5,      #0xF1             @ r5 = 0000 ... 1111 0001
ORR   r6, r4, r5                 @ r6 = 0000 ... 1111 1101 or 0xFD

Try sample

@AND keeps 1 if both inputs are 1 MOV r1, #0x3C @ r1 = 0000 ... 0011 1100 @ #0x6D 0000 ... 0110 1101 AND r2, r1, #0x6D @ r2 = 0000 ... 0010 1100 or 0x2C @ORR keeps 1 from either pattern MOV r4, #0xAC @ r4 = 0000 ... 1010 1100 MOV r5, #0xF1 @ r5 = 0000 ... 1111 0001 ORR r6, r4, r5 @ r6 = 0000 ... 1111 1101 or 0xFD

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